The ability to retrieve data from an external memory device is a functionality commonly implemented in many integrated circuits (IC). Although modern integrated circuit fabrication technology allows instantiation of memory modules internal to the integrated circuit, the cost and the flexibility offered by stand-alone memory units external to an IC remain preferable or even necessary to many IC applications. For example, an IC with configurable circuits such as an FPGA is often designed to load its configuration programming automatically from non-volatile external memory devices such as flash or EEPROMs.
A typical operation between an IC and an external memory device involves the retrieval of data from the external memory to the IC. In order for the IC to correctly sample the retrieved data retrieved from the external memory, the retrieved data must arrive at a sampling register in the IC within a specific timing window (e.g., meeting the sampling register's setup and hold time requirements). Ensuring data arrival within the specific timing window usually requires that the timing delay from a common clock source to the memory device and from the memory device to the integrated circuit be known with sufficient certainty. Unfortunately, unlike signal paths within an IC that can be tightly specified with little uncertainty, the timing delays across external signal paths tend to be loosely specified with significant uncertainty.
These large uncertainties in timing delay place a ceiling on the frequency the IC can access the external memory for data retrieval. As data sampled during uncertainty periods is likely invalid, an IC must sample data in the “eyes” between uncertainty periods. If the IC accesses the external memory at too great a frequency, the periods of uncertainty will crowd out these “eyes” and make sampling valid data impossible. Thus, even though modern external memory devices have greatly improved their maximum operating frequencies, few systems are able to use the improvement in memory devices to improve performance. In fact, very little improvement in performance is possible without first minimizing uncertainty in timing delays.
One technique for reducing the effect of timing uncertainties is to place the memory device as close to the IC as possible. Another technique is to add a delay to the IC's internal clock path in order to delay sampling of the retrieved data. These techniques require hardware alterations that are specific to a particular system, requiring an investment in engineering effort that cannot be reutilized. Furthermore, these techniques only address timing uncertainties that are knowable before the system is built and neglect uncertainties that may arise or disappear during real-time operation of the system. These techniques also treat each individual unit as if they are completely identical with identical attributes, failing to take advantage of individual components in the system that may perform faster with less uncertainty. As a result, systems built using these techniques must operate at frequencies low enough to accommodate the worst performing unit.
Thus, there is a need in the art for an IC that can automatically determine timing delay uncertainties for data retrieval from an external memory device. There is also a need for a method or an apparatus for determining an optimal operating frequency for the data retrieval based on the automatically determined timing uncertainties. There is further a need for a method or an apparatus for determining an optimal sampling time for sampling the retrieved data based on the automatically determined timing uncertainties.